A particularly attractive magnetic bubble memory of the conductor access type is disclosed in my copending application Ser. No. 914,959 filed June 12, 1978. In memories of the type disclosed therein, the movement of magnetic bubbles in a suitable host layer of material is achieved in response to a sequence of current pulses impressed in first and second electrically-conducting layers adjacent the bubble layer. The electrically-conducting layers are separated by an electrically-insulating layer and include like patterns of apertures one pattern offset with respect to the other. The apertures respond to the current pulses to produce successive patterns of magnetic field gradients which move bubble patterns along paths defined by the patterns of apertures.
In a typical memory organization, the paths are arranged in closed loops between which bubble patterns are transferred during operation. The loops are arranged in parallel to recirculate bubbles in what are commonly referred to as minor loops. When a particular address is selected, a bubble patterns is moved into an accessing loop termed a major loop operative to move bubbles to a detector. A bubble generator also couples the major loop to create a replacement bubble pattern for transfer into a selected address. All operations, write, read, transfer and propagation are synchronized to a sequence of propagation pulses derived from a master clock. One skilled in the art will recognize the operation as typical of major-minor bubble memories as described in U.S. Pat. No. 3,618,054 issued Nov. 2, 1971 to P. I. Bonyhard, U. F. Gianola and A. J. Perneski.
Conductor access memories of the type described above do not require increasing amounts of power as the increasingly higher frequencies are realized. But, a number of current reducing techniques are being employed to improve the efficiency of the chip and drive-electronics. For example, new material systems exhibit surprisingly high mobilities, low coercivities and virtually zero magnetostriction. Such materials are very attractive for realizing practical conductor access memories. Also, conductor layer partitioning allows separate operation of major and minor loops leading to a low duty cycle and thus low power requirements.